Buffer vs Inverter in the Clock Tree

• Inverters, because their transition time is shorter. That reduces the crowbar current between the VDD and VSS rails and so cuts power. It is best to keep both available across all drive strengths to achieve good skew and insertion delay.
• Another benefit of inverters in a clock tree is reduced duty-cycle distortion. Cell-library delay models are usually characterised at three corners - worst, typical and best - but other effects are not captured, such as PLL-induced clock jitter and variation in PFET/NFET doping and other physical manufacturing effects.

KEY Inverters are preferred in clock trees - faster transitions, lower crowbar power and less duty-cycle distortion.

Buffers and Inverters Used in CTS

CTS uses buffers or inverters to build the clock tree. The tool identifies them as long as their Boolean function is defined during library preparation. By default CTS will use all buffers and inverters available in the libraries, so it is not necessary to list each one explicitly in the buffer/inverter list.

KEY By default CTS uses all library buffers and inverters whose Boolean function is defined - no explicit list needed.

Clock Tree for Gated Clocks

Historically, separate trees were built for nets driving clock-gating elements and for nets driving clock leaves, diverging at the root of the net. This produced excessive insertion delay and made the clock tree more vulnerable to on-chip variation (OCV). By default the clock tree synthesizer instead tries to tap the gated branches into a lower point in the main tree, sharing more of the tree topology with the non-gated branches by inserting negative-offset branch points earlier in the main tree. This usually inserts fewer buffers, lowers insertion delay and reduces local OCV impact. The tap-in feature should be disabled if it inserts too many buffers or makes the insertion delay too large.