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VLSI Physical Design  ›  Ch 6. PD Tool Inputs & Outputs

Chapter 6

Routing, Antenna & Physical Verification

PD Tool - Inputs and Outputs

Inputs needed to start PD:

  • Technology file (.tf in Synopsys, .techlef in Cadence) - defines units, layers, design rules, vias and the process R and C.
  • Physical libraries (LEF/GDS, or CEL/FRAM views) - abstract layout of macros, standard cells and IO pads, including pin access and blockages.
  • Timing/logical/power libraries (.lib or .db) - timing and power data for every cell.
  • IO/pad file (.tdf or .io) - pad ordering and location, plus VDD/VSS pad and cut-diode instances not present in the netlist.
  • Constraints (.sdc) - area, power and timing requirements.
  • PDEF / DEF (optional) - row and cell placement information.

Outputs the tool generates:

  • SDF - timing data (excluding load).
  • SPEF/DSPF - extracted resistance and capacitance of cells and nets.
  • Routed netlist (.v) - flat or hierarchical connectivity of all cells.
  • GDS - the final physical layout.
  • DEF - row, cell and net placement locations.

KEY In = tech file, LEF/GDS, .lib, IO file, SDC. Out = SDF, SPEF, routed netlist, GDS, DEF.

Non-Default Routing Rules (NDR)

An NDR typically means double width and double spacing. After PnR, if timing, crosstalk or noise violations are hard to fix at the ECO stage, NDRs can be applied during routing.

They are mainly used on special nets such as clock nets, where extra width and spacing improve signal integrity and reduce crosstalk and noise. Double spacing helps against crosstalk; double width helps against