Where a Clock-Gating Cell Is Placed

• Timing - the relevant path starts at the register that produces the enable signal and ends at the clock-gating cell (the ICG or CGC).
• Clock-gating cells (CGCs) are positioned during the placement stage.
• At placement the clock-path delays are still treated as zero.
• So the data-path delay is what effectively decides where the clock-gating cell sits.

KEY Clock-gate placement is driven by data-path timing since clock delays are zero at placement.

Spacing Over Shielding for Clock Nets

• Shielding adds extra ground capacitance to the clock net, which increases its load.
• Shielding also uses up more routing resources.

KEY Spacing beats shielding because shielding adds load capacitance and consumes routing tracks.

Selecting Cells for CTS

• Cells that form the main clock tree.
• Cells that may only be resized (size-only).
• Cells used for inserting delay.

KEY CTS needs main clock-tree cells, size-only cells, and delay-insertion cells.

Fixing Timing on Clock-Gating Paths

• Fix the violation on the data path.
• Reduce the clock insertion delay at the start point, using useful skew or a float-pin value.

KEY Fix clock-gating timing via the data path or by cutting startpoint clock insertion delay.