CCS Timing Model vs NLDM

CCS timing model:

• It resolves the RC-009 warning condition, which arises when the driver's drive resistance is much smaller than the network impedance to ground.
• It handles the Miller effect, dynamic IR drop and multi-voltage analysis more accurately.
• It was developed for deep-submicron nodes to capture process effects that simpler models miss.
• Its driver is modelled as a time-varying current source, which represents high-impedance nets and non-monotonic behaviour accurately.
• Its receiver model uses two capacitance values rather than one lumped cap - one applies up to the input delay threshold, then the load switches to the second value, giving a better approximation when the Miller effect is present.
• Output drivers are modelled with a current source that varies with both time and voltage, with detailed receiver-pin capacitance and output charging currents for each scenario.
• CCS models do not exhibit the long-tail effect.

NLDM model:

• The driver is a Thevenin model - a linear voltage ramp in series with a resistor that smooths the ramp so the waveform resembles a real driver into an RC network.
• When the drive resistance is much smaller than the network impedance to ground, the smoothing weakens and RC delay accuracy drops; PrimeTime then adjusts the drive resistance and issues an RC-009 warning.
• The receiver is a single capacitor; although the value can differ by rise/fall or min/max condition, only one value applies per timing check, so the Miller effect cannot be modelled accurately.
• Delay through a timing arc is characterised from output load capacitance and input transition. In reality the load is capacitance plus interconnect resistance, but NLDM assumes a purely capacitive