• Switching to low-Vt, fast cells (accepting higher gate leakage).
• Using one-hot encoded registers to speed up operation, and physical-design techniques to cut capacitance and wire delay.

KEY Fix paths with logic opt, better placement, pipelining, driver splitting, LVT swaps and DP tweaks.

Cell Delay and Net Delay

A net is the wire connecting standard-cell pins. Cell delay is the timing delay between a cell's input and output pins; net delay is the interconnect delay between the driver pin and the load pin. Stage delay is the sum of the two.

Net delay is the time to charge or discharge the net's parasitics (R, C, L). Without the physical wire the net delay cannot be estimated accurately, since the parasitics depend on the wire's dimensions.

KEY Cell delay = input-to-output of a cell; net delay = driver-to-load interconnect delay; stage = both.

What Cell and Net Delay Depend On

• Input skew / transition.
• Library setup time.
• Library delay model.
• Cell load characteristics.
• Operating conditions (PVT).
• Back-annotated delay.
• Wire load model.
• External delay.

KEY Delay depends on input slew, library model, load, operating conditions, WLM and back-annotation.

Worst Delay and Best Delay

Every gate and net has a minimum and a maximum delay. In STA the maximum delay is the worst delay and the minimum delay is the best delay. Rise and fall delays are also classified into these min and max categories.