Programmable Array Logic (PAL)
A programmable AND array with a fixed OR array — cheaper and faster than a PLA.
Description
A PAL fixes the OR array (each output sums a fixed group of product terms) while keeping the AND array programmable. This loses term sharing but is simpler, faster, and cheaper than a PLA, and often includes output flip-flops with feedback so sequential machines can be built in one device.
- Each output is hard-wired to OR a fixed number of product terms.
- Only the AND array is programmable.
- No product-term sharing between outputs.
- Fewer programmable points → faster and cheaper than a PLA.
- If an output needs more terms than provided, feed one output into another.
- Many PALs include a flip-flop on each output.
- Output feedback into the AND array enables sequential logic / FSMs.
- A programmable output XOR selects polarity.
- This makes a single PAL a small state machine.
- Macrocells generalize this (combinational or registered, per output).
At a glance
What
A device with a programmable AND array and a fixed OR array (fixed terms per output).
Why
Simpler and faster than a PLA; the dominant classic PLD.
How
Program the AND array; each output ORs its own fixed set of product terms.
Where
Glue logic, state machines (with output registers + feedback).
When
When per-output term counts are bounded and sharing isn't needed.
Think of it like…
A PAL is a fixed-menu combo: you customize the toppings (AND terms) but each combo bundles a set number of items (fixed OR) — faster to order than a fully à la carte PLA.
Fixed OR array
- Each output is hard-wired to OR a fixed number of product terms.
- Only the AND array is programmable.
- No product-term sharing between outputs.
- Fewer programmable points → faster and cheaper than a PLA.
- If an output needs more terms than provided, feed one output into another.
Registered outputs
- Many PALs include a flip-flop on each output.
- Output feedback into the AND array enables sequential logic / FSMs.
- A programmable output XOR selects polarity.
- This makes a single PAL a small state machine.
- Macrocells generalize this (combinational or registered, per output).
PAL vs PLA
| PLA | PAL | |
|---|---|---|
| AND array | programmable | programmable |
| OR array | programmable | fixed |
| Term sharing | yes | no |
| Speed/cost | slower | faster/cheaper |
Black-box view
Inputs on the left → outputs on the right · particles show signal direction
Functional / block diagram
Functional blocks · arrows animate in the direction data flows
Real-world applications
The 5 Whys
- 1
Why fix the OR array? Simpler, faster, cheaper silicon.
- 2
Why lose sharing? Acceptable when per-output terms are bounded.
- 3
Why registered outputs? To build FSMs in one chip.
- 4
Why feedback? Present state must re-enter the AND array.
- 5
Root cause: fixing one array trades flexibility for speed and cost.
Cheat sheet
Working principle
- Program the AND array; each output ORs its own fixed set of product terms.
- A device with a programmable AND array and a fixed OR array (fixed terms per output).
Formulas & Boolean expressions
- Output = OR of a fixed term group
- Feedback enables FSMs
Key facts
- Each output is hard-wired to OR a fixed number of product terms.
- Many PALs include a flip-flop on each output.
Why it exists
- Root cause: fixing one array trades flexibility for speed and cost.