Use of TLU-PLUS Files

TLU-PLUS files hold the RC models, which the place-and-route tool uses to compute RC delay.

KEY TLU-PLUS files provide RC models that the tool uses to compute RC delay.

The Mapping File

• A mapping file is an aliasing file that lets another tool understand the metal layers as named in the PD tool.
• It is required by StarRC for parasitic extraction.
• It is also required when dumping a GDS file out of the tool.

KEY A mapping file aliases PD-tool layer names for other tools - needed for StarRC and for GDS dumps.

Creating a Basic SDC

• Import the Verilog netlist into ICC.
• Identify all the clock ports.
• Define clocks on those ports.
• Run check_timing and clear the reported errors.

Then define the IO constraints:

• set_driving_cell on the input ports.
• set_input_transition on the input ports.
• set_load on the output ports.
• set_input_delay on the input ports.

KEY Import the netlist, define clocks, clean check_timing, then add IO constraints (driving cell, transition, load, input delay).

Validating an SDC

Check the multi-cycle paths - for example a setup defined over 3 cycles should have its hold defined over 2 cycles. Check 2-flop synchronizers - they should always have a multi-cycle of 2 for data capture, with the hold check given a multi-cycle of 1. Review every false path declared in the SDC to confirm it is valid.