Factors Behind Setup and Hold Time

Setup and hold time depend on the input data slope, the clock slope, and the output load of the cell.

KEY Setup/hold depend on data slew, clock slew and output load.

Setup and Hold Violations

After data is launched from a flip-flop it reaches the next flop's input with some delay. If that delay makes the data unstable around the capture edge, the setup requirement is not met and the flop can become metastable - a setup violation.

Similarly, if data changes too soon after the capture edge, the hold requirement is broken. Hold violations are functional failures that cannot be tuned away with frequency.

KEY Setup violation = data too late; hold violation = data too early (a true functional failure).

Reasons for Setup or Hold Violations

• A high (slow) clock slope.
• A very fast data transition from the launch flop to the capture flop.
• Excessive clock skew so the second edge is shifted relative to the first, breaking edge alignment.
• Capacitive coupling between nets.
• Underlying design issues.

KEY Causes: bad clock slope, too-fast data, large skew, coupling, and design weaknesses.

Worst Path and Best Path

Between a start and end point many paths exist. The path with the smallest delay is the best, early or minimum path. The path with the largest delay is the worst, late or maximum path.

KEY Best path = minimum delay; worst path = maximum delay between the same endpoints.