KEY Inverting the capture clock makes setup a tight half-cycle path while relaxing hold by an extra half cycle.

Improving Clock Insertion Delay

• Use clock cells with adequate drive strength - avoid low-drive cells.
• Prefer clock inverters over clock buffers.
• Use double-width clock nets - this halves resistance (R' = R/2) while only slightly raising ground capacitance, so the net effect improves insertion delay.
• Place the clock port on a core edge roughly equidistant from all corners.
• Place the first-level clock-gating element near the centre of the design and build the tree from there.
• Slightly relax the max-transition and skew limits.
• Use multi-point CTS: divide the design into four equal regions, route an H-tree from the main clock port to those four points, and add one large clock buffer in each region.
• Disconnect all CP pins from the main clock port.
• Collect the register CP pins in each region, reconnect them to the output of that region's large buffer, and build a normal clock tree from there.
• Use a clock mesh, accepting that it costs more routing resources and power.
• Keep congestion minimal before CTS, otherwise clock nets detour and need many extra cells to fix DRVs, degrading insertion delay.
• Watch for floorplan issues such as missing density screens in macro channels, which let registers be placed there - the CTS engine then adds many clock cells trying to balance those isolated registers against all other leaf pins.
• Consider fishbone CTS.
• Using a single buffer/inverter of proper drive strength helps in MCMM designs by minimising OCV spread across corners; it does not improve insertion delay itself but indirectly reduces violations. Note that using only one cell type is too optimistic - CTS must drive very different