Origin of the Derating Value

• The derating value is set using the library vendor's guidelines and recommendations together with experience from earlier designs.
• PVT variation is the underlying factor that determines the derating factor.

KEY Derate comes from vendor guidance plus past experience and is driven by PVT variation.

Derating the Clock Path

It can be done, but it would not be as accurate as derating the data path, so it is generally avoided.

KEY It is possible but less accurate than data-path derating, so it is avoided.

CRPR in Crosstalk Analysis

• In PrimeTime SI crosstalk analysis, a crosstalk-induced delay change on the common segment of a clock path can be pessimistic, but only for a zero-cycle check, where the same clock edge launches and captures the path. For other path types it is not pessimistic, because the change cannot be assumed identical for the launch and capture clock edges.
• Accordingly, the CRPR algorithm removes crosstalk-induced delays on the common portion of the launch and capture clock paths only when the check is a zero-cycle check, since aggressor switching then affects both the launch and capture signals the same way at the same time.

Cases where CRPR may apply to crosstalk-induced delays include:

• A standard hold check.
• A hold check on a register with Q-bar fed back to D, as in a divide-by-2 clock circuit.
• A hold check with crosstalk feedback due to parasitic capacitance between a register's Q-bar output and D input.
• A hold check on a multicycle path set to zero, where a single clock edge launches and captures with designed-in skew between them.