Functional ECOs (FECOs)

A functional ECO is a Verilog change for some functionality - added ports, modified gate connections - originating from the designer to add features or fix bugs. Its impact depends on design timelines and the scale of change: 2000 net updates means the whole DB must be re-checked (implementation and STA), while adding 10 flops adds timing paths and requires the CTS network to be rebuilt. Inputs are the modified PD Verilog netlist plus supporting material such as a PPT, email or note. Generating the ECOs in TCL for the PD tool can be done by comparing the netlists and dumping the changes as ICC commands, by using a synthesis tool (such as Synopsys DC) with optimization for cell placement and sizing, or by the user generating the ECO with tool commands. Assignment work may include UPF changes for port power assignment and other multi-voltage-domain changes. Verification covers the RTL-to-netlist-to-PD flow, LEC between RTL and synthesis (single-bit and multi-bit), CLP checks similar to LEC, LEC power-aware checks using extra CPF/UPF (IEEE-1801), and multi-bit synthesis where single flops are merged into multi-bit flops. After a FECO, modifications are needed at later stages - RTL is manual effort while PD uses tool-automated commands. The targets are to generate the FECO, implement it, validate STA and PV, and run a gate-to-gate LEC on the implemented FECO netlist. Generating the FECO: build the logical data from the current netlist, compare it with the modified FECO netlist received, and write out the changes as tool commands containing only the logical changes. Implementing the FECO: apply the logical changes, place the added cells (for sequential cells, rebuild CTS per guidelines; for combinational cells, place per timing), then handle DRVs and timing violations, ECO-route the modified nets, and run gate-level LEC and CLP.

KEY A FECO is a designer-driven functional netlist change - generate it by netlist compare, implement, then re-verify with LEC/CLP/STA.