Sequential Programmable Devices (CPLD / FPGA)
Large reprogrammable chips holding whole digital systems — CPLDs and FPGAs.
Description
Modern programmable devices integrate logic and storage at scale. A CPLD is several PAL-like macrocell blocks joined by a programmable interconnect. An FPGA is a sea of small lookup-table logic blocks, flip-flops, block RAM, DSP slices and a rich routing fabric, configured by a bitstream — letting one chip implement nearly any digital system.
- Several PAL-like macrocell blocks on one die.
- A central programmable interconnect links the blocks.
- Non-volatile config; predictable (fixed) timing.
- Good for medium glue logic and control.
- Fewer, larger logic blocks than an FPGA.
- Logic block = a lookup table (LUT) + a flip-flop.
- A LUT stores the truth table of any function of its inputs.
- Programmable routing connects thousands of blocks.
- Hard blocks: block RAM, DSP multipliers, clock managers, I/O.
- Configured by a bitstream (usually loaded from flash at power-up).
At a glance
What
Field-reprogrammable chips (CPLD, FPGA) that hold complete sequential systems.
Why
They give ASIC-like capability with instant, in-field reconfiguration.
How
FPGA: LUTs + flip-flops + routing configured by a downloaded bitstream.
Where
Prototyping, networking, accel, aerospace, anywhere flexible hardware is needed.
When
When you need custom hardware without fabricating a chip.
Think of it like…
An FPGA is a city of empty rooms (logic blocks) and roads (routing): the bitstream furnishes each room and lays the roads, building whatever 'machine-city' your design needs.
CPLD
- Several PAL-like macrocell blocks on one die.
- A central programmable interconnect links the blocks.
- Non-volatile config; predictable (fixed) timing.
- Good for medium glue logic and control.
- Fewer, larger logic blocks than an FPGA.
FPGA
- Logic block = a lookup table (LUT) + a flip-flop.
- A LUT stores the truth table of any function of its inputs.
- Programmable routing connects thousands of blocks.
- Hard blocks: block RAM, DSP multipliers, clock managers, I/O.
- Configured by a bitstream (usually loaded from flash at power-up).
CPLD vs FPGA
| CPLD | FPGA | |
|---|---|---|
| Logic | PAL macrocells | LUT + FF sea |
| Config | non-volatile | SRAM (+ flash) |
| Timing | predictable | routing-dependent |
| Capacity | low–medium | medium–huge |
Black-box view
Inputs on the left → outputs on the right · particles show signal direction
Functional / block diagram
Functional blocks · arrows animate in the direction data flows
Real-world applications
The 5 Whys
- 1
Why programmable devices? Custom hardware without fabricating a chip.
- 2
Why LUTs? A small memory can mimic any logic function.
- 3
Why routing fabric? To wire thousands of blocks into one design.
- 4
Why hard blocks (BRAM/DSP)? Common functions run faster/denser as fixed silicon.
- 5
Root cause: configurable logic + storage + routing = a blank slate for any digital system.
Cheat sheet
Working principle
- FPGA: LUTs + flip-flops + routing configured by a downloaded bitstream.
- Field-reprogrammable chips (CPLD, FPGA) that hold complete sequential systems.
Formulas & Boolean expressions
- k-input LUT stores 2^k config bits
- Any function of k vars fits one LUT
- Logic block = a lookup table (LUT) + a flip-flop.
Key facts
- Several PAL-like macrocell blocks on one die.
- Logic block = a lookup table (LUT) + a flip-flop.
Why it exists
- Root cause: configurable logic + storage + routing = a blank slate for any digital system.