• Critical path.

KEY Designers consider data, async, clock, clock-gating, worst/best, capture/launch and critical paths.

Timing Path - Start and End Points

A timing path is a route that STA analyses to compute path delay from gate delays and net delays. Data is launched at the start point, travels through combinational logic, and the path ends at the first sequential element it reaches (the end point).

When the two endpoints are clocked by different (asynchronous) clocks, setup and hold analysis uses the LCM of the two clock periods to work out the launch and capture edges.

KEY A timing path runs from a launch point through combinational logic to the next sequential end point.

First Stage of Timing Delay

In a synchronous circuit the path starts at the clock pin of the launching flip-flop. The delay from that clock edge to the data appearing at its output is the first stage of delay.

The data then passes through combinational gates and interconnect, each adding its own stage delay, until it reaches the capturing flip-flop, where the path stops. Because the same clock feeds both flops, a clock divergence point is created.

KEY The first stage is the clock-to-output delay of the launching flip-flop.

Types of Timing Paths

• Clock pin of one register to the D pin of another register.
• Primary input to the D pin of a register.
• D pin of a register to a primary output.
• Primary input to primary output through combinational logic only.
• Input to macro input pin, macro input to macro output, and macro output to primary output.