Storage Elements: Latches
Latches store one bit and are level-sensitive — they follow the input while enabled.
Description
A bistable element that holds one bit and is transparent while its enable is active. It is the simplest memory cell — the foundation every flip-flop is built from. Cross-coupled NOR/NAND gates latch a value; an enable gates when it can change.
- Built from two cross-coupled NOR (or NAND) gates.
- S=1 sets Q=1; R=1 resets Q=0; S=R=0 holds.
- S=R=1 is forbidden — both outputs go to the same value (invalid).
- Adds an enable; while enable=1, Q follows D (transparent).
- While enable=0, Q holds — this removes the SR invalid state.
- What: A bistable element that holds one bit and is transparent while its enable is active.
- Why: It is the simplest memory cell — the foundation every flip-flop is built from.
- How: Cross-coupled NOR/NAND gates latch a value; an enable gates when it can change.
- Where: Inside flip-flops, transparent register banks, and some low-power designs.
- When: Level-sensitive storage; replaced by flip-flops when edge timing is needed.
At a glance
What
A bistable element that holds one bit and is transparent while its enable is active.
Why
It is the simplest memory cell — the foundation every flip-flop is built from.
How
Cross-coupled NOR/NAND gates latch a value; an enable gates when it can change.
Where
Inside flip-flops, transparent register banks, and some low-power designs.
When
Level-sensitive storage; replaced by flip-flops when edge timing is needed.
Think of it like…
A latch is like a door held open by a doorstop (enable): while propped, people (the input) walk straight through; remove the stop and whoever's inside stays inside.
SR latch
- Built from two cross-coupled NOR (or NAND) gates.
- S=1 sets Q=1; R=1 resets Q=0; S=R=0 holds.
- S=R=1 is forbidden — both outputs go to the same value (invalid).
D latch (transparent)
- Adds an enable; while enable=1, Q follows D (transparent).
- While enable=0, Q holds — this removes the SR invalid state.
SR latch behavior
| S | R | Q⁺ |
|---|---|---|
| 0 | 0 | Q (hold) |
| 0 | 1 | 0 (reset) |
| 1 | 0 | 1 (set) |
| 1 | 1 | invalid |
Black-box view
Inputs on the left → outputs on the right · particles show signal direction
SR / D latch behavior (rising-edge demo)
▶ live simulatorSet inputs, then Run for a live clock (or Step one edge) and watch Q on the waveform.
| S | R | Q⁺ | note |
|---|---|---|---|
| 0 | 0 | Q | no change |
| 0 | 1 | 0 | reset |
| 1 | 0 | 1 | set |
| 1 | 1 | ? | invalid |
Characteristic equation: Q⁺ = S + R′Q (SR = 0)
The 5 Whys
- 1
Why latches? The simplest one-bit memory.
- 2
Why cross-coupled gates? The feedback makes the value self-sustaining.
- 3
Why an enable? To control when the stored bit may change.
- 4
Why move beyond latches? Level-sensitivity causes timing hazards in big designs.
- 5
Root cause: a bistable feedback loop is the atom of digital memory.
Cheat sheet
Working principle
- Cross-coupled NOR/NAND gates latch a value; an enable gates when it can change.
- A bistable element that holds one bit and is transparent while its enable is active.
Formulas & Boolean expressions
- S=1 sets Q=1; R=1 resets Q=0; S=R=0 holds.
- S=R=1 is forbidden — both outputs go to the same value (invalid).
- Adds an enable; while enable=1, Q follows D (transparent).
- While enable=0, Q holds — this removes the SR invalid state.
Key facts
- Built from two cross-coupled NOR (or NAND) gates.
- Adds an enable; while enable=1, Q follows D (transparent).
Why it exists
- Root cause: a bistable feedback loop is the atom of digital memory.