Register Transfer Level (RTL) Notation
The shorthand R2 ← R1 meaning 'copy R1 into R2 on the clock edge'.
Description
RTL notation expresses operations as register transfers: a destination register, an arrow, and a source expression, optionally guarded by a control condition. R2 ← R1 means load R2 with R1 at the next clock edge; conditions like 'if (T1): R ← R + 1' tie transfers to control states.
- Registers named by capital letters (R1, AR, PC).
- Transfer: R2 ← R1 (parallel load on the clock edge).
- Condition: 'if (P): R ← R + 1' performs only when P is true.
- Concurrent transfers separated by commas happen together.
- Operations: add (+), shift, logic, increment, etc.
- ← implies a clocked register with a load/enable.
- The source expression implies functional units (adder, mux).
- The condition implies a control signal from the FSM.
- Bus notation shows shared transfer paths.
- Microoperations are the atomic transfers.
At a glance
What
A compact notation for register transfers and their control conditions.
Why
It precisely states which data moves where, and under what condition.
How
dest ← source, optionally prefixed by a control condition/state.
Where
Datapath specification and the basis of RTL HDL.
When
When formalizing operations before coding HDL.
Think of it like…
RTL notation is a stage direction: 'on cue (clock), move the prop (data) from table R1 to table R2'.
Notation elements
- Registers named by capital letters (R1, AR, PC).
- Transfer: R2 ← R1 (parallel load on the clock edge).
- Condition: 'if (P): R ← R + 1' performs only when P is true.
- Concurrent transfers separated by commas happen together.
- Operations: add (+), shift, logic, increment, etc.
Implied hardware
- ← implies a clocked register with a load/enable.
- The source expression implies functional units (adder, mux).
- The condition implies a control signal from the FSM.
- Bus notation shows shared transfer paths.
- Microoperations are the atomic transfers.
Microoperation types
| Type | Example |
|---|---|
| Transfer | R2 ← R1 |
| Arithmetic | R ← R + 1 |
| Logic | R ← R1 ∧ R2 |
| Shift | R ← shr R |
Real-world applications
The 5 Whys
- 1
Why a notation? Precisely state data movement.
- 2
Why the arrow? It implies clocked loading.
- 3
Why conditions? Transfers happen only in certain states.
- 4
Why microoperations? Atomic, composable steps.
- 5
Root cause: a transfer notation maps one-to-one onto clocked datapath hardware.
Cheat sheet
Working principle
- dest ← source, optionally prefixed by a control condition/state.
- A compact notation for register transfers and their control conditions.
Formulas & Boolean expressions
- dest ← source (on clock edge)
- if (cond): transfer
- Transfer = R2 ← R1
- Arithmetic = R ← R + 1
- Logic = R ← R1 ∧ R2
- Shift = R ← shr R
Key facts
- Registers named by capital letters (R1, AR, PC).
- ← implies a clocked register with a load/enable.
Why it exists
- Root cause: a transfer notation maps one-to-one onto clocked datapath hardware.