KEY set_case_analysis forces a constant on a port in the SDC to fix the design's operating mode.

The Need for Critical Range

• It saves optimization runtime.
• Since combinational logic is shared across many paths, the tool does not have to work on every single path.

KEY Critical range saves runtime by limiting optimization to paths within a slack window of the worst path.

Critical, False and Multicycle Paths

STA exhaustively explores every timing path. The critical path is the timing-sensitive functional path with the longest delay in the design - if its delay exceeds the clock period, timing is violated. A false path is a path along which data is never actually transferred from start to end; it is functionally invalid and is often inserted deliberately to relate asynchronous logic. A multicycle path is one where data legitimately takes more than one clock cycle to travel from start to end point.

KEY Critical = longest real path; false = never exercised; multicycle = needs more than one cycle.

False Path in STA

A false path is a path that does not need to be optimised during timing analysis - it does not have to complete launch and capture within the same clock cycle, so the timing optimization tool ignores it.

KEY A false path need not meet single-cycle timing, so the tool skips optimising it.

The Multicycle Path Concept

Normally setup and hold happen within a single clock pulse, but sometimes the combinational delay between launch and capture spans more than one cycle - that path is a multicycle path. On a multicycle path the capture flop's edge becomes active only after