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Volume II: Digital Logic  ›  Register Transfer Level Design

Design Example (ASMD Chart)

An ASM chart annotated with the register transfers each state performs — links control to datapath.

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Description

An ASMD (ASM-with-Datapath) chart annotates each state with the register transfers (datapath operations) that occur in it. It is the bridge between the control ASM and the datapath, showing exactly which transfers each control state triggers — the complete RTL specification.

  • Each ASMD state lists the register transfers performed in it.
  • Datapath status signals (e.g. zero flag) drive decision boxes.
  • Control outputs in each state enable those transfers.
  • Transfers are written beside the state, not inside the FSM logic.
  • The chart fully specifies both halves of the system.
  • State boxes → controller FSM states.
  • Listed transfers → datapath register/mux/ALU control.
  • Decision inputs → datapath status lines.
  • One ASMD → one datapath + one controller.
  • Directly codeable as two HDL blocks.

At a glance

What

An ASM chart whose states are annotated with their register transfers.

Why

It unifies control and datapath into one verifiable specification.

How

Each state box lists its RTL transfers; decisions test datapath status.

Where

The core design artifact for an RTL system.

When

After splitting the design into datapath + controller.

Think of it like…

An ASMD chart is a recipe that, at each step, also tells you exactly which bowl to pour into — control steps and the actual ingredient moves on one page.

Control + datapath together

  • Each ASMD state lists the register transfers performed in it.
  • Datapath status signals (e.g. zero flag) drive decision boxes.
  • Control outputs in each state enable those transfers.
  • Transfers are written beside the state, not inside the FSM logic.
  • The chart fully specifies both halves of the system.

From ASMD to hardware

  • State boxes → controller FSM states.
  • Listed transfers → datapath register/mux/ALU control.
  • Decision inputs → datapath status lines.
  • One ASMD → one datapath + one controller.
  • Directly codeable as two HDL blocks.

ASMD annotations

In a stateMeans
R ← R + 1datapath transfer
assert loadcontrol output
if (Z)test datapath status

Functional / block diagram

StartStatus
Controller (FSM)
Datapath (regs+ALU)
DoneResult

Functional blocks · arrows animate in the direction data flows

Real-world applications

Sequential multiplierDividersAny control+datapath design

The 5 Whys

  1. 1

    Why ASMD? Unify control + datapath in one chart.

  2. 2

    Why annotate transfers? Show what each state does to data.

  3. 3

    Why status decisions? Datapath feeds back to control.

  4. 4

    Why one chart? Single source of truth for the design.

  5. 5

    Root cause: control states + their transfers fully define an RTL machine.

Cheat sheet

Working principle

  • Each state box lists its RTL transfers; decisions test datapath status.
  • An ASM chart whose states are annotated with their register transfers.

Formulas & Boolean expressions

  • R ← R + 1 = datapath transfer
  • assert load = control output
  • if (Z) = test datapath status

Key facts

  • Each ASMD state lists the register transfers performed in it.
  • State boxes → controller FSM states.

Why it exists

  • Root cause: control states + their transfers fully define an RTL machine.
PrevAlgorithmic State Machines
NextHDL of Design Example