Stage Where Hold Fixing Happens
- Preferred approach: fix violations down to about -0.020 at post-CTS, then clean up all remaining violations at post-route.
- Alternative: fix all hold violations only at post-route.
KEY Hold is fixed partly at post-CTS and fully at post-route, or entirely at post-route.
Details to Capture at Each Stage
- Starting utilization.
- Block height and width.
- Total die area.
- Zero-interconnect timing (report_qor).
- Macro orientation.
- Cell VT distribution (LVT, HVT) - all critical paths should be LVT; query with
get_cells -hier * -filter {ref_name=~*LVT*}. - Standard cell count and area - found via
get_cells -hier * -filter {mask_layout_type=~*std*},get_attributeandforeach_in_collection. - Macro count and area.
- Buffer and inverter count and area.
- Clock buffer and inverter count and area.
- Hold buffer count and area.
KEY Capture utilization, area, ZIC timing, macro orientation, VT mix, and cell/buffer counts at each stage.
MCP-2 vs Inserting a Register
- If a path has N multicycle paths, you get data only once every N clock cycles.
- If a path is pipelined with N registers in between, you still get data every cycle, but with a latency of N clock cycles.
On use cases, taking an MCP is easier than registering, but the choice between MCP and pipelining depends on the data-flow requirement of the design.