Why Reduce Clock Skew

• Reducing clock skew is not only a performance concern - it is also a manufacturing concern.
• Scan-based testing, currently the most common way to structurally test chips for manufacturing defects, needs minimum skew so scan vectors can shift error-free to detect stuck-at and delay faults.
• Hold failures at the best-case PVT corner are common in scan circuits because there are usually no logic gates between one flop's output and the scan input of the next flop in the chain.
• Managing and reducing clock skew often resolves these hold failures.

KEY Low skew is needed for performance and for scan-based manufacturing test, and it cures scan-chain hold failures.

Pre-CTS Checks

• Hierarchical pins should not be defined as a clock source.
• A generated clock must have a valid master clock source. It is invalid when: the master clock named in create_generated_clock does not exist, that master clock does not drive the source pin of the generated clock; or the source pin is driven by multiple clocks and some masters are not specified with create_generated_clock.
• No clock - master or generated - should have no sinks.
• There should be no looping clocks.
• There should be no cascaded clock with an un-synthesized clock tree in its fan-out.
• If multiple-clocks-per-register propagation is not enabled, the design should not contain overlapping clocks.
• Clock-tree exceptions should not be ignored.
• A stop pin or float pin defined on an output pin is a problem.

KEY Pre-CTS checks: valid clock sources and master clocks, no loops, no sinkless clocks, and clean clock exceptions.