• Only the architecture team can clarify these constraints when there is any doubt.
• It is a timing constraint that instructs the STA tool to check setup and hold over the specified number of cycles.
• By default the setup check is performed one cycle apart.
• By default the hold check is performed between the current launch active edge and the previous capture active edge.

KEY A multi-cycle path constraint tells STA to check setup/hold over more cycles when data-path delay exceeds the clock period.

Analysing Multi-Cycle Path Problems

• Sketch the launch and capture waveforms assuming an ideal clock.
• Identify and mark the active edges on both the launch and capture clocks.
• Lock down the current active launch edge as the reference.
• On the capture side, count out the number of cycles given by the multi-cycle constraint.
• Pick the setup-check edge according to the specified multi-cycle value.
• For the setup check, move forward by the stated number of cycles.
• For the hold check, move backward by (number of cycles minus one).

KEY Draw the waveforms, fix the launch edge, then shift forward N cycles for setup and back N-1 for hold.

set_case_analysis

Example usage: set_case_analysis 0 [get_ports SCAN_EN].

• It is defined in the SDC file.
• It propagates a fixed logic value up to a MUX so the tool can decide the mode of operation.
• To find the assignment, check the case_analysis statements in the SDC - for example by going to the design data directory and running grep 'case_analy' on the .sdc files, or grepping the full path to those files.