KEY Reset forces a known start state; the two types are synchronous and asynchronous.

Synchronous Reset

A synchronous reset is sampled with the clock - it only takes effect at an active clock edge, so the reset pulse must be stretched to be visible during the clock.

Advantages: gives a fully synchronous circuit, reduces clock-glitch problems, deassertion completes within one clock, meeting reset recovery time.

Disadvantages: unsuitable for clock-gated circuits, slows the process, needs the clock to be always present, the reset pulse must be wide enough to be seen, and it can interfere with other signals during timing analysis and synthesis.

KEY Synchronous reset is clock-sampled - clean and glitch-safe, but needs a running clock.

Asynchronous Reset

An asynchronous reset takes effect as soon as the reset signal is asserted, independent of the clock - no need to wait for a clock edge.

Advantages: no need for the clock to be active, faster operation, reset has the highest priority.

Disadvantages: metastability can occur (especially at deassertion), clock-glitch risk. It is used when the chip must be reset before the clock is available.

KEY Asynchronous reset acts immediately without a clock, but risks metastability at deassertion.

Reset Assertion and Deassertion

Reset assertion is applying the reset - the reset signal is logically true. Reset deassertion is releasing the reset - the reset signal is logically false.

With asynchronous reset, deassertion can cause metastability because some flip-flops may leave reset before others, so assertion and