a defined number of cycles, and data is launched less often than every cycle. The designer gives the timing tool an exception flag so it postpones the launch and capture checks accordingly.

KEY A multicycle path legitimately spans several cycles; an exception flag tells STA to relax the check.

Setting Up a Multicycle Path in the Tool

When launch and capture genuinely need more than one clock cycle, it is declared with a multicycle exception, e.g. set_multicycle_path n -from <start> -to <end>, where 'n' is the number of clock cycles allowed. This instructs the timing tool to verify the path against the relaxed constraint.

KEY Use set_multicycle_path n -from -to to tell STA the path may take n cycles.

On-Chip Variation (OCV)

Ideally every device on a chip would run at one speed and interconnects would sit at a single corner, but manufacturing variation makes the speed non-uniform - effective transistor channel length and width vary, so identically drawn devices can differ. The main on-chip variations are: channel length, temperature, IR drop, transistor width, threshold voltage, and interconnect variation.

KEY OCV is the spread in device speed across one die from process, temperature and IR-drop variation.

Global vs Local Variation

Global chip-to-chip variation is the performance difference between separate dies; it is modelled as operating corners. Local on-chip variation is the performance difference between transistors within the same die; it is modelled as an extra derating factor added to skew calculations. Its sources include oxide thickness, transistor channel dimensions, and the number of doping atoms.