Synthesizing a Clock Tree

• Single clock - perform normal synthesis and optimization.
• Multiple clocks - synthesize each clock separately.
• Multiple clocks with domain crossing - synthesize each clock separately and then balance the skew between them.

KEY Synthesize one clock normally, multiple clocks separately, and balance skew when domains cross.

Number of Clocks in the Project

• This is specific to the particular project.
• The more clocks there are, the more challenging the design becomes.

KEY The clock count is project-specific - more clocks mean a harder design.

Handling Multiple Clocks

For multiple clocks: synthesize each one separately, balance the skew, then optimize the clock tree. The difficulty depends on whether the clocks come from separate external sources or from a PLL. If the clocks come from separate sources (asynchronous, from different pads or pins), balancing skew between those sources is challenging. If they come from a PLL (synchronous), skew balancing is comparatively easy.

KEY Synthesize each clock separately and balance skew - harder for asynchronous sources, easier from a PLL.

Buffers in the Clock Tree (Revisited)

Buffers are used to balance skew, that is, to equalise the flop-to-flop clock delay.

KEY Clock-tree buffers balance skew by equalising flop-to-flop delay.

48 MHz vs 500 MHz Clock - Which Is Harder

The 500 MHz clock, because its shorter clock period makes it more tightly constrained than the 48 MHz clock.