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Volume II: Digital Logic  ›  Boolean Algebra & Logic Gates

Integrated Circuits

How gates are packed onto chips — from a handful (SSI) to billions (VLSI).

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Description

Chips that integrate many gates onto a single piece of silicon. Integration slashes size, cost, power, and delay versus discrete gates. Fabricate transistors and interconnect together; classify by gate count and logic family.

  • SSI: a few gates. MSI: tens. LSI: thousands. VLSI/ULSI: millions–billions.
  • Higher integration improves speed and power per function.
  • CMOS dominates due to very low static power.
  • Key specs: fan-out, propagation delay, noise margin, power dissipation.
  • What: Chips that integrate many gates onto a single piece of silicon.
  • Why: Integration slashes size, cost, power, and delay versus discrete gates.
  • How: Fabricate transistors and interconnect together; classify by gate count and logic family.
  • Where: Every modern electronic product, from microcontrollers to GPUs.
  • When: The default realization of any non-trivial digital design.
  • Analogy — From a few houses (SSI) to a megacity on one chip (VLSI): same bricks, just packed denser and wired shorter, so everything runs faster and cheaper.

At a glance

What

Chips that integrate many gates onto a single piece of silicon.

Why

Integration slashes size, cost, power, and delay versus discrete gates.

How

Fabricate transistors and interconnect together; classify by gate count and logic family.

Where

Every modern electronic product, from microcontrollers to GPUs.

When

The default realization of any non-trivial digital design.

Think of it like…

From a few houses (SSI) to a megacity on one chip (VLSI): same bricks, just packed denser and wired shorter, so everything runs faster and cheaper.

Integration levels

  • SSI: a few gates. MSI: tens. LSI: thousands. VLSI/ULSI: millions–billions.
  • Higher integration improves speed and power per function.

Logic families & parameters

  • CMOS dominates due to very low static power.
  • Key specs: fan-out, propagation delay, noise margin, power dissipation.

Integration scale

LevelGates (approx.)Era / example
SSI1–10basic gate chips
MSI10–100adders, mux ICs
LSI100–10kearly microprocessors
VLSI10k–10M+modern CPUs
ULSI>10MGPUs, SoCs

The 5 Whys

  1. 1

    Why integrate gates onto one chip? To cut size, cost, and delay.

  2. 2

    Why does delay drop? On-chip wires are far shorter than board traces.

  3. 3

    Why does CMOS dominate? It draws almost no power when idle.

  4. 4

    Why does idle power matter? Battery life and heat limit big designs.

  5. 5

    Root cause: integration economics (Moore's law) made dense, low-power CMOS the universal choice.

Cheat sheet

Working principle

  • Fabricate transistors and interconnect together; classify by gate count and logic family.
  • Chips that integrate many gates onto a single piece of silicon.

Key facts

  • SSI: a few gates. MSI: tens. LSI: thousands. VLSI/ULSI: millions–billions.
  • CMOS dominates due to very low static power.

Why it exists

  • Root cause: integration economics (Moore's law) made dense, low-power CMOS the universal choice.
PrevDigital Logic Gates
NextIntroduction