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Volume II: Digital Logic  ›  Register Transfer Level Design

Design with Multiplexers

Use muxes to choose each register's next value instead of many control gates.

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Description

Mux-based RTL design routes each register's input through a multiplexer whose select lines come from the controller. Instead of scattered enable gates, one mux per register cleanly selects among possible sources (hold, load, increment, shift), making the datapath regular and the control simple.

  • Each register input is driven by a multiplexer.
  • Mux inputs = the candidate next values (hold, load, R+1, shift…).
  • Controller select lines pick the active source per state.
  • Replaces a tangle of per-source enable gates.
  • Makes the datapath regular and scalable.
  • Clear mapping: control state → mux select.
  • Easy to add a new source (extra mux input).
  • Uniform structure aids layout and timing.
  • Decouples 'what sources exist' from 'when chosen'.
  • Common in CPU register-file write paths.

At a glance

What

A datapath style where a mux selects each register's next-state source.

Why

It centralizes source selection and simplifies control.

How

Each register input = mux of its candidate sources; controller drives selects.

Where

Regular datapaths and CPU register inputs.

When

When a register has several possible next values.

Think of it like…

A mux-fed register is a single faucet with a selector dial: turn the dial (select) to choose which pipe (source) fills the basin (register).

Mux per register

  • Each register input is driven by a multiplexer.
  • Mux inputs = the candidate next values (hold, load, R+1, shift…).
  • Controller select lines pick the active source per state.
  • Replaces a tangle of per-source enable gates.
  • Makes the datapath regular and scalable.

Benefits

  • Clear mapping: control state → mux select.
  • Easy to add a new source (extra mux input).
  • Uniform structure aids layout and timing.
  • Decouples 'what sources exist' from 'when chosen'.
  • Common in CPU register-file write paths.

Mux select → action

SelR next
00R (hold)
01data (load)
10R + 1
11shr R

Black-box view

sourcessel (from control)Mux-fed registerblack boxR next

Inputs on the left → outputs on the right · particles show signal direction

Mux selecting a register's next value

▶ live simulator
D01D10D21D30MUX4:11YS10S00

Select = 00 (0) → routes D0 to Y. Click any D or S to toggle.

Real-world applications

CPU register inputsRegular datapaths

The 5 Whys

  1. 1

    Why muxes? Centralize next-value selection.

  2. 2

    Why one per register? Each register picks its own source.

  3. 3

    Why simpler control? Select lines replace enable webs.

  4. 4

    Why scalable? Add a source = add a mux input.

  5. 5

    Root cause: a mux turns 'which source' into a clean select signal.

Cheat sheet

Working principle

  • Each register input = mux of its candidate sources; controller drives selects.
  • A datapath style where a mux selects each register's next-state source.

Formulas & Boolean expressions

  • Mux inputs = the candidate next values (hold, load, R+1, shift…).
  • 00 = R (hold)
  • 01 = data (load)
  • 10 = R + 1
  • 11 = shr R

Key facts

  • Each register input is driven by a multiplexer.
  • Clear mapping: control state → mux select.

Why it exists

  • Root cause: a mux turns 'which source' into a clean select signal.
PrevHDL of Binary Multiplier
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