path to gain setup slack, watching neighbouring paths. Hold fixes during CTS (data must be slowed down):

• Increase drive strength of data-path gates, or insert/remove buffers.
• Use higher-Vt cells, route on higher metal layers, or increase the launch flop's clk-to-Q delay. KEY Placement: path groups, bounds, timing-driven place_opt. CTS: sizing, Vt swap, buffering, useful skew.

Setup Before CTS, Hold After CTS Until post-CTS the clock is treated as ideal, reaching every sink instantly. So before CTS the only thing we can control is the data path - we make sure it fits within one clock period. The clock period is a constant, leaving data-path delay as the variable to optimise, so setup is the focus before CTS. Hold depends on the minimum data-path delay versus the clock edge. With an ideal clock reaching every sink in zero time, the minimum data delay is almost always larger than the hold requirement, so there is little point analysing hold until the real clock-network delay exists - i.e. after CTS. KEY Pre-CTS only the data path is real, so optimise setup; hold needs real clock delay, so it waits for CTS.

STA on a Latch-Based Design Yes. Latch-based designs usually use two-phase, non-overlapping clocks to control successive registers in a data path, and the timing engine can use time borrowing to relax the constraints on successive paths. Consider three level-sensitive latches, transparent when the G input is high: L1 and L3 controlled by PH1, L2 by PH2. A rising edge launches data from a latch output and a falling edge captures data at a latch input; assume zero latch setup and delay for the example. For the path L1 to L2, the rising edge of PH1 launches the data, which must arrive at L2 before PH2's closing edge at time=20 (Setup 1). Depending on the L1-to-L2 delay, the data may arrive before or after PH2's opening edge at time=10; arrival after time=20 is a violation.