Achieving Zero Skew

Zero skew would make every flop trigger at exactly the same instant, which causes a large simultaneous current draw and therefore higher peak power consumption.

KEY Zero skew triggers all flops together, spiking current and raising power.

HVT vs ULVT for a Setup-Critical Hold Fix

HVT cells show larger delay variation across PVT corners - across different voltages and temperatures, including temperature inversion - because the Vgs-Vt drive margin varies a lot. ULVT cells vary less, so ULVT is the better choice for fixing hold on a path that is also setup-critical.

KEY ULVT cells vary less across corners than HVT, so use ULVT for hold on setup-critical paths.

Factors Affecting Threshold Voltage

• VDD (VDS) - as VDS rises, the drain depletion region grows, the effective channel length shrinks, and Vt changes (drops).
• Substrate body voltage - as the body potential rises above 0V, Vt decreases, following Vt = Vt(sb=0) - K[sqrt(Phi + Vsb) - sqrt(Phi)].
• Channel length - Vt changes in proportion to channel length.
• Gate oxide thickness - a thinner gate oxide lowers Vt, since a channel forms at a smaller Vgs when the oxide is thin.
• Temperature - higher temperature lowers Vt, following Vt(T) = Vt(Tr) - K(T - Tr), where Tr is room temperature and K is a constant.
• Channel doping concentration - Vt decreases as channel doping increases.
• Substrate doping - heavier substrate doping raises Vt (for example, more doping in the P-substrate of an NMOS increases its Vt).

KEY Vt depends on VDS, body bias, channel length, oxide thickness, temperature and doping levels.