Hold uncertainty: pre-CTS = skew + extra hold margin; post-CTS = extra hold margin.

KEY Uncertainty is a clock-edge window; hold uncertainty omits jitter and post-CTS values shrink as real skew becomes known.

Buffers vs Inverters for CTS

An inverter takes less area and can drive a longer distance, but it switches more; it is good for maintaining pulse width and pulse period.

• For the same drive strength, an inverter has more current-driving capability than a buffer, so inverters are faster than buffers.
• Fewer inverters than buffers are needed for the same net length, so insertion delay is better with inverters, which indirectly reduces the OCV effect on timing since OCV is proportional to insertion delay.
• Because switching is higher in an inverter-based clock tree, it may increase OCV.
• Inverters maintain a 50% duty cycle and have a regenerative property.
• Inverters have a better noise-cancellation effect than buffers.

KEY Inverters are smaller, faster and better at duty cycle and noise than buffers, giving lower insertion delay despite more switching.

Clock Uncertainty After Post-CTS

• Jitter is not part of OCV; it comes from PLL noise, so uncertainties and OCV derating factors must be kept as separate entities.
• OCV derating is a path-based margin that only covers PVT variation. The process part covers transistor channel-length and gate-oxide-thickness variation from mask, CMP and etch variations - two instances of the same library cell placed in different locations can have different delays.
• Temperature variations: junction temperature, clock-cell switching activity and high-density areas can create higher temperatures, so cell delays vary.
• Voltage variations: for some cells the voltage drops because of IR-drop issues, often in higher-density regions.