its output pin.
- It is the input-to-output delay when a near-zero slew is applied at the input and the output sees no load, and it is mainly caused by the internal capacitance of the gate's transistors.
- It is largely independent of transistor size, because making the transistors larger also increases the internal capacitance. Net delay (also called wire delay):
- Net delay is the difference between when a signal is first applied to a net and when it reaches the other devices on that net.
- It is caused by the finite resistance and capacitance of the net, and is a function of Rnet and (Cnet + Cpin). KEY Cell delay is the input-to-output 50% delay through a gate; net delay is the RC interconnect delay along a wire.
Delay Models
- Linear Delay Model (LDM).
- Composite Current Source (CCS) modeling. KEY Common delay models are the Linear Delay Model and the Composite Current Source model.
Setup and Hold Equations
- Setup:
Tlaunch + Tclk_q_max + Tcombo_max <= Tcapture + Tclk - Tsetup. - Hold:
Tlaunch + Tclk_q_min + Tcombo_min >= Tcapture + Thold.
