KEY Setup compares max data arrival against the capture edge minus setup; hold compares min data arrival against capture plus hold.

Factors Behind Flip-Flop Setup Time The setup time of a flip-flop depends on the transition (slew) at its D pin and the transition at its clock pin. KEY Flip-flop setup time depends on the D-pin transition and the clock transition.

Latency and Its Types Source latency:

• Also called source latency, it is the delay from the clock origin point to the point where the clock is defined in the design.
• It is the delay from the clock source to the start of the clock tree, that is the clock definition point.
• In other words, the time the clock takes to travel from its ideal waveform origin to the clock definition point. Network latency:
• Also known as insertion delay or network latency, it is the delay from the clock definition point to the clock pin of a register.
• It is the time a rising or falling clock edge takes to travel from the clock definition point to a register's clock pin. KEY Latency has two parts - source latency (origin to definition point) and network latency (definition point to register clock pin).

Types of Delay in ASIC Design Common delay types in ASIC/VLSI design include source delay/latency, network delay/latency, insertion delay, transition delay/slew, path delay, net/wire/interconnect delay, propagation delay, phase delay, cell delay, intrinsic delay, extrinsic delay, input delay, output delay, exit delay, latency (pre/post CTS) and uncertainty (pre/post CTS). Gate (cell) delay:

• Transistors inside a gate need a finite time to switch, so a change