corresponding 50% point of the output transition; it is the time for an event to pass through a gate or net, taken as the average of rise and fall, Tpd = (Tphl + Tplh)/2. Phase delay:

• The same as insertion delay. Intrinsic delay:
• The delay internal to a gate, measured between an input/output pair with near-zero input slew and no output load; it is caused by the internal transistor capacitance and is largely independent of transistor size, since bigger transistors also add more internal capacitance. Extrinsic delay:
• The same as wire/net/interconnect delay or flight time - the delay associated with interconnect from one cell's output pin to the next cell's input pin. Input delay:
• The time at which data arrives at a block's input pin from external logic, relative to the reference clock. Output delay:
• The time the external logic needs, before which data must arrive at the block's output pin, relative to the reference clock. Exit delay:
• The delay along the longest (critical) path between a clock pad input and an output; it sets the maximum operating frequency of the design. Latency (pre/post CTS):
• The sum of source latency and network latency; an estimated latency is used during synthesis (pre-CTS) and the propagated latency is used after CTS. Uncertainty (pre/post CTS):
• The amount of skew plus variation in the clock-edge arrival; pre-CTS it covers skew and jitter, and post-CTS a smaller margin of skew plus jitter remains. Unateness: