• A function is positive unate if a rising input causes the output to rise or stay unchanged; negative unate means the output is the inverted version of the input (for example an inverter).
• A clock is positive unate if a rising source edge produces only a rising edge at the register clock pin, negative unate if it produces only a falling edge, and not unate if the clock sense is ambiguous, such as a clock passing through an XOR gate. Jitter:
• The short-term deviation of a signal from its ideal position in time - the variation of the clock period from edge to edge, which can be plus or minus.
• Sources of jitter include PLL internal circuitry, random thermal noise from a crystal, other resonating devices, mechanical crystal vibration, signal transmitters, traces and cables, connectors and receivers. KEY VLSI delays span source, network, insertion, transition, path, net, propagation, cell, intrinsic, extrinsic, I/O and exit delays, plus latency and uncertainty.

Fixing Setup with a Frozen Base

• Check for detours on the nets in that path, then remove and re-route them.
• Route on a higher metal layer, or promote the path's nets to higher layers.
• Fix any crosstalk issue on the data path.
• Insert a buffer by converting nearby fortune/spare cells.
• Restructure the logic - rearrange timing-critical nets of an AND gate away from its ground side and timing-critical nets of an OR gate away from its power side, so non-critical nets come first and do not load the critical nets, reducing delay. KEY With placement frozen, fix setup by re-routing detours, layer promotion, fixing crosstalk, using spare-cell buffers and logic restructuring.