switches; in the steady on/off states Cgd is negligible. But during the on-to-off and off-to-on transitions the inverter is briefly amplifying, so the Miller effect becomes significant, raising the input capacitance, slowing the transition and increasing propagation delay.

In short, the Miller effect of Cgd reduces the highest operating frequency of a CMOS inverter.
The Miller effect can be reduced with a cascode connection (common-source in series with common-gate), which improves input-output isolation - there is no direct output-to-input coupling - eliminating the Miller effect and giving much higher bandwidth.
Device engineers can also reduce Cgd technologically by minimizing the overlap area between the gate and drain.
If the receiver cell is a high-drive single-stage cell (such as an inverter) and is lightly loaded by a short net, the fast output transition couples strongly back to the input interconnect through the Miller capacitance, much like crosstalk, distorting the input signal and delaying its transition.
In that situation the receiver behaves like an aggressor driver even with no external crosstalk, so it degrades the cell's operating frequency.

Diagram 1

KEY The Miller effect amplifies Cgd at the input during transitions, slowing the cell - mitigated by cascode or less gate-drain overlap.

Avoiding Crosstalk

Crosstalk grows with greater parallel run length between nets, so the fixes target that:

Reduce parallel run length by changing the metal layer.