• Add more spacing to lower the coupling capacitance.
• Insert buffers to strengthen the net.
• Use report_timing -crosstalk_delay to analyze the impact.
• Use report_noise_calculation to evaluate the noise.

KEY Reduce crosstalk by cutting parallel length, adding spacing and buffers, and analyzing with crosstalk/noise reports.

Why Crosstalk Is a Major Concern

• Its polarity is not fixed, so it can affect both setup and hold paths.
• Crosstalk can lengthen the delay of a setup path.
• At the same time it can shorten the delay of a hold path.
• Because of this, correcting crosstalk repairs both setup and hold paths simultaneously.

KEY Crosstalk has variable polarity, hurting setup and hold at once, so fixing it cures both.

Shielding and Spacing - Hard or Soft Constraints

• They are soft constraints - the tool applies them only where space permits.
• In congested regions they are commonly skipped.
• Typically more than 70 percent of clock nets do get NDR applied.

KEY Shielding/spacing are soft constraints, honoured where space allows, often ~70% of clock nets.

Signal Integrity Issues

Signal integrity issues are a set of design problems including crosstalk, cross-coupling, electromigration and IR drop. A small variation on one part of the die can affect the whole chip.

Because wires run close to one another separated only by insulator, a change in one wire's signal can alter the signal on a coupled wire - so the signal loses its integrity.

KEY SI issues = crosstalk, coupling, EM and IR drop - a wire's signal disturbing its neighbours.