KEY A PMOS header is generally preferred for power gating because it leaks less, switches gently and accepts reverse body bias cheaply.

PMOS Footer and NMOS Header Limitation

• If an NMOS is used as the header (drain on VDD, source feeding the load and the shutdown block), it can only pass VDD minus VT. The shutdown block therefore receives a reduced supply, which degrades the performance of the cells inside it.
• If a PMOS is used as the footer (source on the shutdown block, drain on ground), it can only pull the source down to VT. The shutdown block is then never cleanly tied to ground.
• In both arrangements the voltage swing is attenuated, which is why the polarity is chosen the other way around.

KEY NMOS header and PMOS footer attenuate the rail by VT, so the supply or ground is never clean.

Isolation Cells Across Stacked Voltage Domains

For a signal travelling from V1 toward V3: no isolation cell is needed where it leaves V1 and enters V2, because V1 is always on. When V2 is off and V3 is on, one isolation cell is required between V2 and V3.

The principle is that an isolation cell is needed at each crossing from a switchable (possibly off) domain into another domain, so the count depends on which domains can be powered down along the path.