isolation cells sit on every on/off boundary

KEY Isolation is needed only at crossings out of a switchable domain - one cell between V2 and V3 in this case.

Swapping PMOS and NMOS in an Inverter

After swapping, the NMOS has its drain on VDD and source on the load CL, and the PMOS has its drain on ground and source on the load CL. Assume Vtn = Vtp = Vt and that CL starts at 0V.

When Vin = VDD: for the NMOS, Vgs = VDD, which exceeds Vt, so it turns on and charges CL toward VDD. Once the output reaches VDD - Vt, the NMOS Vgs drops to Vt and the NMOS turns off. So the output settles at VDD - Vt, attenuated by Vt. The PMOS sees Vgs = VDD, which is greater than -Vt, so it stays off.

When Vin = 0: the NMOS sees Vgs = -(VDD - Vt), so it is off. The PMOS sees Vgs = -(VDD - Vt), which is less than -Vt, so it turns on and discharges CL toward 0V. It stops when the output reaches Vt, at which point Vgs = -Vt and the PMOS turns off. So the output settles at Vt when Vin is 0.

Summary: the output is VDD - Vt when Vin = VDD and Vt when Vin = 0. The circuit no longer acts as a pure buffer - it behaves as a partial (attenuated) buffer.

KEY Swapping the transistors gives a degraded output (VDD-Vt high, Vt low) - it works only as a partial, attenuated buffer.