Reducing Short-Circuit Current in an Inverter

Short-circuit current is large when the output load capacitance is low and the input rise/fall time is large. To reduce short-circuit power dissipation, the input and output rise/fall times should be of the same order. The average short-circuit power follows Pavg = (1/12)[K * f (VDD - Vthn - |Vthp|)^3].

In general short-circuit current is proportional to frequency and voltage - it occurs when the input transitions from 0 to 1 or 1 to 0, so a faster-toggling clock produces more short-circuit current.

KEY Match input and output transition times; short-circuit current rises with slow inputs, light loads, frequency and voltage.

Zero-Bit Retention Flop

Every retention flop needs isolation on its clock pin and reset pin. This isolation can be built into the retention flop itself, or implemented as a separate isolation cell connected to the CK and RST pins.

Building it into the flop reduces implementation complexity. Using separate isolation cells consumes less area because one isolation cell can be shared across several retention flops, but it adds implementation complexity. This shared-isolation approach is what is called a zero-bit retention flop.

KEY A zero-bit retention flop uses shared external isolation cells on CK/RST instead of built-in isolation, saving area at the cost of complexity.

Implementing a Zero-Bit Retention Flop

First, if the incoming netlist has any isolation cells on the CK or RST pins of the retention flops, remove them.

After high-fanout net synthesis, take the last buffer driving the reset pin of the retention flop and convert it into an iso-high cell - this handles reset-pin isolation.

Before CTS, collect the fan-in of the CK pins of all retention flops - these are ICG outputs - and insert an iso-low cell on those outputs. Place a dont-touch on the outputs of those isolation cells, then let the